(1)Field of the Invention
The present invention relates to a ferroelectric memory device using a ferroelectric material and a method of reading data from the ferroelectric memory device.
(2)Description of the Prior Art
In recent years, non-volatile memories, which have a function of retaining the storage even when the power is turned off, have been realized using a ferroelectric material with a hysteresis characteristic such as lead zirconate titanate (PZT:Pb(Zr.sub.x Ti.sub.1-x)O.sub.3) in memory cells. The operation of a non-volatile memory circuit using a general ferroelectric material (hereinafter referred to as a ferroelectric memory) will be described in the following.
FIG. 1 illustrates an example of a memory cell circuit comprising a single transistor and a single ferroelectric capacitor (hereinafter referred to as a 1T/1C type memory cell). In this memory cell circuit, transistor TC in memory cell MC has a gate terminal connected to word line WL, a source terminal connected to one terminal of ferroelectric capacitor FC, and a drain terminal connected to bit line BL. The other terminal of ferroelectric capacitor FC is connected to plate line PL.
In the memory cell circuit shown in FIG. 1, a voltage on word line WL controls transistor TC to turn on and off to determine whether the memory cell is selected or unselected. Data is written into and read from ferroelectric capacitor FC via a bit line.
FIG. 2 illustrates the relationship of spontaneous polarization charge Q of ferroelectric capacitor FC with regard to voltage V across both electrodes of ferroelectric capacitor FC. For example, the states of polarization of ferroelectric capacitor FC designated by A, B correspond to data "1", data "0" respectively. Upon applying voltage Ve across both electrodes of ferroelectric capacitor FC, charge Q1 shown in FIG. 2 is outputted from ferroelectric capacitor FC onto bit line BL in the case of data "1", while charge Q0 shown in FIG. 2 is outputted from ferroelectric capacitor FC onto bit line BL in the case of data "0". By discriminating the difference between charge Q1 and charge Q0 thus outputted, storage of binary information can be achieved.
As described above, a memory device using a ferroelectric capacitor retains data by the polarization occurring within the ferroelectric material even when an external voltage across the ferroelectric capacitor is equal to zero, thereby providing a characteristic of a so-called non-volatile storage operation capable of retaining storage even when the power is turned off.
FIG. 3 illustrates a circuit column portion in memory cell array using the above-mentioned 1T/1C type memory cell as shown in FIG. 1. This memory cell array comprises memory cells MC11-MCn1, MC12-MCn2, transistor TC11 and ferroelectric capacitor FC11 included in memory cell MC11, bit line precharge circuits PC1, PC2, reference voltage generating circuits DC11, DC21, DC12, DC22, and sense amplifier circuit SAMP2 serving as a differential amplifier circuit. In FIG. 3, word lines are designated by WLL1-WLn; plate lines by PL1-PLn; bit lines by BL1, BL1, BL2, BL2; a bit line precharge control signal line by PBL; a bit precharge voltage line by VBL; reference voltage generating circuit control signal lines by DWL1, DWL2; and a sense amplifier circuit control signal line by SE.
A signal voltage supplied from the memory cell, for example, when memory cell MC11 is selected, appears on bit line BL1. It can be determined whether the signal voltage appearing on bit line BL1 corresponds to "0" or "1" by generating a voltage serving as a reference voltage on bit line BL1 which forms a pair with bit line BL1 and using a differential amplifier circuit such as a sense amplifier circuit. In this case, the reference voltage is typically set to an intermediate voltage value between a read signal voltage corresponding to data "0" and a read signal voltage corresponding to data "1".
FIG. 4 illustrates operation timing charts for the memory cell array shown in FIG. 3 described above. These timing charts are based on a method described in the proceedings for International Solid-State Circuits Conference (ISSCC), February, 1994, pp268-269. In the following, the reading operation and writing operation for the ferroelectric memory, when word line WL1 is selected and memory cell MC11 is to be considered, is described with reference to FIGS. 3 and 4. It should be noted that in operation timing charts, also in the other drawings later described, a level corresponding to the high level "H" is either a power supply voltage supplied from the external of the memory device or a voltage generated in a voltage generating circuit provided in the memory device, while a level corresponding to the low level "L" is a ground voltage, unless otherwise remarked. For reference, the states of polarization of ferroelectric capacitor FC11 at the end of each of periods 1-6 in FIG. 4 are shown at the bottom of FIG. 4.
In periods 1-3 in FIG. 4, an operation is performed for reading data from the memory cell. First, bit line precharge control signal PBL is changed to the low level in period 1 to release bit line precharge. Here, bit line precharge voltage VBP is set at a ground potential.
Next, word line WL1 and plate line PL1 are respectively changed to the high level to output data from memory cell MC11 onto bit line BL1 in period 2. Although data is outputted from memory cell MC12 onto bit line BL2 at the same time, description for the operation associated with memory cell MC12 and bit line BL2 is omitted to avoid confusion since the operation of memory cell MC12 is similar to that of memory cell MC11. At this point, the data signal outputted from memory cell MC11 depends on the polarization state of ferroelectric capacitor FC11. FIG. 4 illustrates how data "1" is read by way of example. On the other hand, a proper reference voltage is generated by reference voltage generating circuit DC21 on bit line BL1 which forms a pair with bit line BL1 with control signal DWL2.
After generating the reference voltage, in period 3, sense amplifier circuit control signal SE is activated to differentially amplify the difference in voltage between bit line BL1 and bit line BL1 by sense amplifier circuit SAMP1.
In subsequent periods 4-6, the operations are performed for writing back the data, which have been read in periods 1-3, to memory cell MC11. This data write-back operation is needed because the data in ferroelectric capacitor FC11 have been collapsed in period 2. When data inputted from the outside of the ferroelectric memory device is written into a memory cell, a voltage corresponding to desired data is set on bit line BL1 and bit line BL1 in period 3 and then the operations in period 4 onward are performed.
In period 4, plate line PL1 is changed to the low level. In the subsequent period 5, sense amplifier circuit control signal SE is changed to the low level to deactivate sense amplifier circuit SAMP1, and bit line precharge control signal PBL is changed to the high level to change the bit line level to the ground potential. Thus, the polarization of ferroelectric capacitor FC11 can be recovered to the state of period 1 before data is read. Finally, word line W1 is changed to the low level to turn off transistor TC11, thereby completing the access operation to memory cell MC11.
Now, the relationship between the above-mentioned circuit operation and the characteristics of a ferroelectric capacitor is described. For example, the state in period 2 in FIG. 4, where word line WL1 is changed to the high level to cause conduction in transistor TC11 and plate line PL1 is changed to high level corresponds to the state in which voltage -Ve is applied to the ferroelectric capacitor (assume herein that the direction from the plate line to the bit line is in the positive direction of the voltage). At this point, charge Q1 or charge Q0 is outputted onto bit line BL1. In this state, however, the polarization of the ferroelectric capacitor is at h point in FIG. 2 when either one of data "1" or "0" is stored, so that it can not be determined whether the data corresponds to data "1" or "0". Thus, an operation is required for applying a voltage of +Ve or 0 to the ferroelectric capacitor respectively depending on the read "1" or "0" data and writing the data back to the memory cell. This operation corresponds to that in period 4 in FIG. 4.
In the example shown in FIGS. 3 and 4, both plate line and bit line are driven between the low level and the high level to allow voltages both in positive and negative directions to be applied across both electrodes of the ferroelectric capacitor, thereby allowing for either one of data "0" and "1" to be written to the ferroelectric capacitor. On the other hand, there is an operating method in which the plate line is set at an intermediate potential between the low level and the high level, and the bit line is driven between the low level and the high level, thereby allowing voltages both in positive and negative directions to be applied across both electrodes of the ferroelectric capacitor.
An example of the operation method mentioned above is described in the proceedings for International Solid-State Circuits Conference (ISSCC), February, 1996, pp368-369. FIG. 5 illustrates a circuit diagram of a portion of an example of a ferroelectric memory cell array employing the above-mentioned operating method and FIG. 6 illustrates operation timing charts thereof. In the following description, the same reference numerals and symbols are used to designate the same components of those illustrated in FIGS. 3 and 4 and the description thereon is omitted unless additional description is not particularly required.
The memory cell array illustrated in FIG. 5 is provided with bit line balance control circuits EB1, EB2. A bit line balance control signal line is designated by EBL in FIG. 5. The states of polarization of ferroelectric capacitor FC11 at the end of each of the periods 1-6 are shown at the bottom of FIG. 6 for reference. The reading operation and writing operation will be hereinafter described for the case where word line WL1 is selected and memory cell MC11 is to be considered with reference to FIG. 5 and FIG. 6, similarly to the description for FIGS. 3 and 4.
First, bit line precharge control signal PBL is changed to the low level to release the bit line precharge in period 1. Bit line precharge voltage V.sub.BP is at a ground potential similarly to the example of FIGS. 3 and 4.
Next, in period 2, word line WL1 is changed to the high level to output data from memory cell MC11 onto bit line B11. The operation of FIG. 6 differs from that of FIG. 4 in that plate line PL1 remains at an intermediate potential (hereinafter referred to as voltage Vm). Since the bit line precharge level is at the ground potential and the plate line is at the intermediate potential, a voltage substantially equal to voltage -Vm, assuming that a direction from the plate line to the bit line is a positive direction of the voltage, is applied across both electrodes of ferroelectric capacitor FC11 when transistor TC11 is in a conducted state in period 2. Then, signal charge corresponding to the state of the polarization is read from ferroelectric capacitor FC11 onto bit line BL1. At the same time, a proper reference voltage is generated by reference voltage generating circuit DC21 on bit line BL1 which forms a pair with bit line BL1. In the subsequent period 3, sense amplifier circuit control signal SE is activated to differentially amplify the difference in voltage between bit line BL1 and bit line BL1 by sense amplifier circuit SAMP1.
When data inputted from the outside of a memory device is written into the memory cell, a voltage corresponding to desired data is set on bit line BL1 and bit line BL1 in period 4 and then operations in period 5 onward are performed.
In period 5, sense amplifier circuit control signal SE is changed to the low level to deactivate sense amplifier circuit SAMP1. Furthermore, bit line balance control signal EBL is changed to the high level to set bit line BL1 at the same intermediate potential as plate line PL1. Thus, the polarization of ferroelectric capacitor FC11 can be recovered to the state in period 1 before data is read.
After word line WL1 is changed to the low level to turn off transistor FC11 in period 6, bit lines BL1, BL1 are changed to the ground potential in period 7, thereby completing the access operation to memory cell MC11.
The signal charge read from the ferroelectric capacitor depends on a voltage value applied across both electrodes of the ferroelectric capacitor. Generally, as the voltage value applied across both electrodes is higher, the signal charge is increased. In the operation of the ferroelectric memory device as that in the example described above, the voltage applied across both electrodes of the ferroelectric capacitor is related to a plate line setting voltage and a bit line voltage amplitude.
The plate line setting voltage and the bit line voltage amplitude may be set at any value as long as the sense amplifier can normally sense and amplify a signal voltage read from the ferroelectric capacitor. For example, there are methods in which the voltage for setting the plate line is one half the level of the power supply voltage and the bit line amplitude is at a level between the ground potential and the power supply voltage. The power supply voltage may be either a voltage supplied from the outside of the memory device or a voltage generated in a voltage generating circuit in the memory device.
As described above, in the operation of the ferroelectric memory device, a voltage serving as reference need be generated when the data read from the memory cell is amplified in the sense amplifier circuit. A specific example of such a reference voltage generating circuit is described in the above-mentioned literature (proceedings for International Solid-State Circuits Conference (ISSCC), February, 1994, pp368-369). FIG. 7 illustrates the circuit and FIG. 8 illustrates operation timing charts associated with the circuit.
In FIG. 7, the memory cell array unit has sense amplifier circuit SAMP1 comprising CMOS inverters cross-connected to each other and reference voltage generating circuits DC11, DC21. Reference voltage generating circuits DC11, DC12 have transistors DTC11, DTC21 and ferroelectric capacitors DFC11, DFC21 in respective cells, and further have transistors DTR11, DTR21, each of which is provided for compensating for a potential at a node where the transistor and the ferroelectric capacitor are connected to each other in a dummy memory cell. These reference voltage generating circuits DC11, DC21 are also referred to as dummy memory cells since they have a similar configuration to that of a 1T/1C type memory cell, based on a circuit comprising a transistor and a ferroelectric capacitor. In FIG. 7, a signal line for controlling transistor DTR11 and transistor DTR21 is indicated by CDWL and signal lines for controlling the sense amplifier circuit are indicated by SAP, SAN respectively.
An essential point of the method of generating a reference voltage with the dummy memory cell shown in FIG. 7 is that the Q-V hysteresis characteristic of ferroelectric capacitor FC11 in the memory cell and the Q-V hysteresis characteristic of ferroelectric capacitor DFC11 in the dummy memory cell are set to have a relationship as shown in FIG. 9. In FIG. 9, a smaller hysteresis curve represents ferroelectric capacitor FC11. Similarly to the example in FIG. 2, -Qr (cell) point and +Qr (cell) point are made to correspond to data "0" and "1", respectively.
When plate line PL1 is driven from the low level to the high level in the circuit shown in FIG. 7 (period 2 in FIG. 8), a voltage outputted from memory cell MC11 onto bit line BL1 is equal to voltage V.sub.0 in FIG. 9 when data "0" has been stored in ferroelectric capacitor FC11 while the voltage is equal to voltage V.sub.1 in FIG. 9 when data "1" has been stored in ferroelectric capacitor FC11. It should be noted that voltage V.sub.0 corresponds to the distance from an intersection of a straight line passing through (-Vcc, -Qr(cell)) with the slope of CB (parasitic capacitance of bit line BL1) and the hysteresis curve for ferroelectric capacitor FC11 to the straight line V=-Vcc, and voltage V.sub.1 corresponds to the distance from an intersection of a straight line passing through (-Vcc, +Qr(cell)) with the slope of CB and the hysteresis curve for ferroelectric capacitor FC11 to the straight line V=-Vcc. On the other hand, when the characteristic for capacitor DFC11 in the dummy memory cell is represented by a larger hysteresis curve in FIG. 9 and capacitor DFC11 always has data "0" stored therein, a voltage, which is supplied onto bit line BL1 when DPL in FIG. 7 is driven from the low level to the high level, is equal to voltage V.sub.REF in FIG. 9 as is the case of above-mentioned ferroelectric capacitor FC11. In the hysteresis characteristic shown in FIG. 9, the following relationship is satisfied. EQU V.sub.0 &lt;V.sub.REF &lt;V.sub.1 ( 1)
Thus, sense amplifier SAMP1 can determine whether the data read from memory cell MC11 corresponds to data "0" or "1".
The foregoing proceedings for ISSCC February, 1994, page 268 describes that the hysteresis characteristic curve for above-mentioned capacitor DFC11 or the like can be changed in shape by changing the size of the ferroelectric capacitor.
In the prior art method of generating a reference voltage in the ferroelectric memory device as described above, however, the signal charge corresponding to the reference voltage is generated by adjusting the size of the ferroelectric capacitor in the dummy memory cell so that the ferroelectric capacitor in the dummy memory cell and the ferroelectric capacitor in the memory cell may have different shapes from each other. Thus, the prior art method of generating a reference voltage has a disadvantage that a generated reference voltage is easily affected by variations in characteristics of the ferroelectric capacitors. For example, when the shapes of the hysteresis characteristic curves for ferroelectric capacitor FC11 and capacitor DFC11 are changed due to variations in manufacturing such that the value of voltage VREF is not an intermediate value between voltage V.sub.0 and voltage V.sub.1 in FIG. 9, a normal reference voltage can not be generated, thereby causing malfunction.
Additionally, ferroelectric materials generally have a characteristic referred to as fatigue characteristic. This is a characteristic wherein the charge during inversed polarization (charge corresponding to charge Q1 in FIG. 2) is reduced as polarization inversion is repeated as shown in FIG. 10. The fatigue characteristic causes the voltage value for voltage V.sub.1 to be lowered as the reading/writing operations for data "1" are repeated, finally leading to the disadvantage of reducing the margin for reading data "1".